1. Field of the Invention
The present invention pertains to the field of memory access in a computing or other processing system. More particularly, the present invention pertains to the field of throttling, or reducing the throughput of, high priority accesses to memory.
2. Description of Related Art
Overall computer system performance may be enhanced by ensuring that all devices in the system which need to gain access to shared resources can do so. If regular access is not ensured, unchecked monopolization of system resources may result. Such monopolization may undesirably sacrifice the performance of components and/or applications which experience more limited access to certain resources. For example, if graphics processing is allowed to monopolize memory access, other peripheral devices or even a central processing unit may be unable to gain sufficient memory access to maintain reasonable performance during the graphics processing.
Many prior art arbitration techniques are designed to avoid bus agent "starvation" (i.e., the bus agent having its functions significantly limited by its inability to access a resource). Such techniques include the use of round-robin or time-sliced scheduling which allows each requesting bus agent access to utilize a resource for a certain amount of time or for a certain number of transactions. Other prior art techniques may implement round robin scheduling in a more elaborate fashion, giving certain bus agents larger time slices or larger numbers of transactions.
Some arbitration algorithms, however, allow certain high priority transactions to take precedence over other types of transactions which seek access to a particular resource. For example, a device making a high priority memory access request may be granted access to memory regardless of other pending requests for memory access. Such preferred access may be prone to abuse if left unchecked. For example, a device that exclusively or extensively utilizes high priority memory access commands may exhibit impressive performance; however, the performance of other devices utilizing lower priority memory access commands may be impacted. As referred to herein, the terms command or memory access command may be used to indicate any type of request signal or command which indicates that a device is requesting that some transaction with memory be performed.
One example of a bus protocol that includes high priority memory access commands which may take precedence over other memory access commands is described in the Accelerated Graphics Port (A.G.P.) Interface Specification, Revision 1.0, Jul. 31, 1996, available from Intel Corporation of Santa Clara, Calif. The A.G.P. specification defines a protocol that uses a set of commands to provide high bandwidth transactions between a bus master (typically a graphics accelerator) and main memory. The transactions include normal and high priority read and write commands of varying lengths.
The high priority A.G.P. commands (also known as expedite commands) may be either reads or writes, either of which can take precedence over other system memory access commands. For example, a typical system includes an arbiter (often located in a component commonly known as a "north bridge") to arbitrate access to system memory. The arbiter receives memory access commands from one or more processors on a host bus. The arbiter also receives memory access commands from devices on a peripheral components interconnect (PCI) bus, as well as A.G.P. commands from an A.G.P. device. A.G.P. expedite commands are typically given priority over PCI and host bus memory requests according to the A.G.P. specification. The PCI bus is described by the PCI Specification available from the PCI Special Interest Group (SIG) in Hillsboro, Oreg.
Abuse of this preference for A.G.P. expedite commands may adversely affect overall system performance. For example, a system vendor wishing to showcase graphics performance may allow a graphics processor connected via the A.G.P. port to use expedite commands for many different types of transactions. While graphics performance may improve, other applications may suffer considerably, especially when such other applications are executed in a multi-tasking environment with graphically intensive applications. Thus, a graphics benchmark may be bolstered, while the overall system appeal may suffer due to lackluster performance in other categories.
Accordingly, a need exists to reduce the probability that a particular monopolistic bus agent capable of making high priority requests will unduly impact system performance. The prior art does not provide a mechanism to throttle high priority memory accesses to preserve system performance. In other words, the prior art lacks a mechanism to control the percentage of memory accesses which are high priority memory accesses in a system where such high priority memory accesses normally are preferred over other memory accesses. Such overriding of the preference for high priority commands may help ensure proper system performance across a variety of applications.